Operating System - Paging Hardware

What is Paging Hardware?

Paging hardware is the physical and logical support in a computer system that enables the use of paging as a memory management technique. It works together with the operating system to translate logical (virtual) addresses into physical addresses using page tables.

1. Page Table

• A data structure used to map virtual pages to physical frames.

• Stored in memory.

• Each entry contains:

  • Frame number

  • Control bits (e.g., valid/invalid, protection)

2. Page Table Base Register (PTBR)

• Holds the starting address of the page table in memory.

• The CPU uses this register to locate the page table for address translation.

3. Page Number and Offset

• When a program accesses memory, the logical address is divided into:

  • Page number – Index into the page table.

  • Offset – Position within the page.

4. Memory Management Unit (MMU)

• A hardware component that performs the translation from a logical address to a physical address.

• Uses the page table and PTBR during translation.

Example of Address Translation:

Assume:

• Logical address = 2050

• Page size = 1024 bytes
  → Page number = 2 (2050 ÷ 1024)
  → Offset = 2 (2050 % 1024)

The MMU:

• Uses Page Table Base Register (PTBR) to find the page table.

• Looks up entry for Page 2 → finds Frame 5

• Computes physical address = Frame 5 × 1024 + Offset = 5120 + 2 = 5122

 Optimizations in Paging Hardware:

 Translation Lookaside Buffer (TLB):

• A cache that stores recent page table entries.

• Speeds up translation by avoiding memory access to the page table.

 Multilevel Paging:

• Used when the page table is large.

• Divides the page table into levels to reduce memory overhead.